1. Field of the Invention
The invention relates to metal-oxide-semiconductor field effect transistors (MOSFETs) and more particularly to transistor structures having very low junction capacitance, and methods of making same.
2. Background
Advances in semiconductor process technology and digital system architecture have led to integrated circuits having increased operating frequencies. Unfortunately, higher operating frequencies result in undesirable increases in power consumption. Power consumption is a significant problem in integrated circuit design generally, and particularly in large scale, high speed products such as processors and microprocessors.
Nonetheless, the trend of integrating more functions on a single substrate while operating at ever higher frequencies goes on unabated.
One way to improve integrated circuit performance, is by reducing the loading capacitance of MOSFETs. Transistor loading capacitance generally has three components, intrinsic gate capacitance, overlap capacitance, and junction capacitance. To reduce junction capacitance, MOSFETs have been constructed on an insulating substrate. This is often referred to as silicon-on-insulator (SOI). Typical SOI processes reduce junction capacitance by isolating junctions from the substrate by interposing a thick buried oxide layer. However, short-channel MOSFETs constructed with thick buried oxide isolation layers tend to have poor punch-through characteristics, poor short-channel characteristics and other effects related to the floating body.
What is needed is a structure having reduced junction capacitance while maintaining good device characteristics. What is further needed is a method of manufacturing such a structure.
Briefly, a MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions.
In a further aspect of the invention, a process for forming a MOSFET having an isolated source and drain, includes forming a recess in a shallow trench isolation (STI) insulator material that surrounds a pillar of silicon which is contiguous with the substrate, forming a silicon region within the recess, and then completing the operations needed to form a MOSFET, resulting in a MOSFET with a source and drain isolated from the body by STI insulation.